A storage system, for example, receives a write request from a host computer and writes data targeted by the write request (write target data) to a storage device, or receives a read request from the host computer, reads the data targeted by the read request from the storage device, and sends it to the host computer.
In such a storage system, a cache memory, for temporarily storing data to be written to the storage device according to the write request or temporarily storing data read from the storage device according to the read request, is installed.
For this cache memory, for example a DRAM (Dynamic Random Access Memory), of which high-speed access (read and write) is possible, is used. For such a DRAM, the unit price per storage capacity increases as the access speed becomes higher. Also the unit price of the DRAM per storage capacity is higher than other memories, such as a flash memory.
If the storage capacity of the cache memory is increased, the response performance to the access from the host computer improves, but the manufacturing cost required for a cache memory increases. Therefore in a general storage system, for which cost aspect must be considered, the cache memory has only a relatively small and limited storage capacity.
In a storage system having a cache memory, a technology of a storage system comprising a memory for storing data the same as data in a cache memory, installed in a connection unit (bus switch) which communicably connects a communication interface, a cache memory and a storage device interface, so as to decrease the response time to access, has been disclosed (e.g. Japanese Patent Application Laid-Open No. 2005-115603).
According to the technology disclosed in Japanese Patent Application Laid-Open No. 2005-115603, a memory is in the connection unit for communicably connecting the communication interface, cache memory unit and storage device interface. This means that if a plurality of functional units attempt to access the data stored in the memory, some functional units must wait for the completion of access by another functional unit, which makes processing efficiency poor, and may even slow down the response time to access. Also the connection unit performs access processing to memory, so the connection between each unit may slow down the response time.